The development of information technology has resulted in a significant increase in the need for data storage.
The state of the art comprises a number of memory circuits, and in particular volatile memory. Due to the increased need for data storage in nearly any application, it is required to get a large set of memory circuits in order to satisfy these needs.
Typically one distinguishes memories as a function of the nature of the memory cell. In static memories, the memory cell retains information to be stored without time limitation, where with dynamic memories information retention is transitory and needs to be periodically refreshed. One classifies memory circuits as a function of the particular architecture which the memory cell uses and, in particular, single port memory, double port memory, FIFO (first in first out) memory, and also shift registers.
The more recent applications call for high density and cheap memory circuits.
Miniaturization of electronic circuits is a first step toward the increase of the density of memory circuits.
Nevertheless, it is desirable to provide memory circuits using a limited set of transistors for every memory cell, as well as an optimal micro architecture of these transistors. That will also enable an increase in the circuit density.
Memories that are built in an array are well known and used because they allow individual addressing of each memory cell.
Shift register memories have limited use compared to memory arrays, but they offer a higher level of integration because their access is decreased so the required resources to implement the access are decreased.
That difference explains the better memory density of nonvolatile memory based on a NAND architecture compared to those based on a NOR architecture.
FIG. 1 shows a conventional structure of a shift register memory as described in U.S. Pat. No. 5,806,084. That structure is based on a shift register made of a cascade of memory elements or buffers connected one to another. FIG. 1 illustrates two buffer circuits 11 and 12, generally made of inverters, separated by propagation transistors 13 and 14 that are used to control propagation of information from one circuit to the other. Such a memory structure is operated as follows. When for example propagation transistor 13 is closed, stage 12 is then connected to the previous one, which achieves the propagation of information from stage 11 to stage 12. When propagation transistor 13 is open, stage 12 is then disconnected from the previous one and behaves like an information retention point that keeps that information during a period of time that is a function of the internal capacity of that circuit.
This memory structure requires a set of 3 transistors per elementary stage, with two of opposite type (inverters are typically made of two MOS transistors of opposite types, P and N, each with specific sources and drains).
That represents a limitation in density increase and it is desirable to solve that problem and to reduce further the obstruction of each elementary stage.